Projects

project_and_non_project_mode

VHDL

No description.

Image-Accellerator

SystemVerilog

This project involve the CNN but it is done through designing the chip which will handle everything during the time of the image capturing

FPGA_master_class_lab1

Verilog

In this lab we are implementing the ALU for OR,AND,XOR,and XNOR. Then the result of the ALU is displayed on the 7segment display board of the Urbana board

Mini-Lab-Project-on-Verilog

Verilog

This project is all about creating, a generator which generate the power of 3 numbers and send through FIFO to the Memory Controller then Memory. We have used the AXI-STREAM interface

axiMemoryMapped_lab

Verilog

The focus of this lab is communication between master and slave components through an AXI memory- mapped protocol. Your task consists of designing modules and testbenches for the master component, the bus, and the two slave components.

Counter

Verilog

No description.

MUX-logic-gate

Verilog

Hardware designing using verilog

Designing_RAM_in_Verilog

Verilog

No description.