My Open Source Projects

In this lab we are implementing the ALU for OR,AND,XOR,and XNOR. Then the result of the ALU is displayed on the 7segment display board of the Urbana board

This project is all about creating, a generator which generate the power of 3 numbers and send through FIFO to the Memory Controller then Memory. We have used the AXI-STREAM interface

This project involve the CNN but it is done through designing the chip which will handle everything during the time of the image capturing

The focus of this lab is communication between master and slave components through an AXI memory- mapped protocol. Your task consists of designing modules and testbenches for the master component, the bus, and the two slave components.

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Hardware designing using verilog